`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:36:38 11/23/2011 
// Design Name: 
// Module Name:    Filtr 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module filtrDA(
	input signed[7:0] signal,
	output  signed [8:0] filtered_sig,	
	
	input clk,
	input reset
    );
	
    reg signed [7:0] r [0:8];
	reg signed [23:0] sum;
	integer i;
	wire signed [8:0] t0, t1, t2, t3, t4;
	wire signed[15:0] y0,y1,y2,y3,y4,y5,y6,y7,y8;
	wire signed[15:0] y0r,y1r,y2r,y3r,y4r,y5r,y6r,y7r,y8r;
	wire signed[4:0] x0, x1, x2, x3, x4, x5, x6, x7,x8;
	
	reg signed [17:0] lev_a_1;
	reg signed [19:0] lev_a_2;
	reg signed [21:0] lev_a_3;
	reg signed [23:0] lev_a_4, lev_b_2, lev_b_3, lev_a_5;
	reg signed [20:0] lev_b_1;


	
	lut2  l0(.table_in(x0), .table_out(y0));
	lut2  l1(.table_in(x1), .table_out(y1));
	lut2  l2(.table_in(x2), .table_out(y2));
	lut2  l3(.table_in(x3), .table_out(y3));
	lut2  l4(.table_in(x4), .table_out(y4));
	lut2  l5(.table_in(x5), .table_out(y5));
	lut2  l6(.table_in(x6), .table_out(y6));
	lut2  l7(.table_in(x7), .table_out(y7));
	lut2  l8(.table_in(x8), .table_out(y8));
	
	
	
	 always @(posedge clk) begin
		if(reset) begin
			for(i=0; i<=8; i=i+1) begin
				r[i]<=0;
			end
		end
		else begin
			for(i=8; i>=1; i=i-1) begin
				r[i]<=r[i-1];
			end
			r[0]<=signal;
		end //if reset
	 end
	 
	 
	assign t0=r[0]+r[8];
	assign t1=r[1]+r[7];
	assign t2=r[2]+r[6];
	assign t3=r[3]+r[5];
	assign t4=r[4];
	
	assign x0={t4[0],t3[0],t2[0],t1[0],t0[0]};
	assign x1={t4[1],t3[1],t2[1],t1[1],t0[1]};
	assign x2={t4[2],t3[2],t2[2],t1[2],t0[2]};
	assign x3={t4[3],t3[3],t2[3],t1[3],t0[3]};
	assign x4={t4[4],t3[4],t2[4],t1[4],t0[4]};
	assign x5={t4[5],t3[5],t2[5],t1[5],t0[5]};
	assign x6={t4[6],t3[6],t2[6],t1[6],t0[6]};
	assign x7={t4[7],t3[7],t2[7],t1[7],t0[7]};
	assign x8={t4[8],t3[8],t2[8],t1[8],t0[8]};

	always @(posedge clk) begin
		if(reset) begin
			 lev_a_1 <= 0;
			 lev_a_2 <= 0;
			 lev_a_3 <= 0;
			 lev_a_4 <= 0;
			 lev_a_5 <= 0;
			
			 lev_b_1 <=0;
			 lev_b_2 <= 0;
			 lev_b_3 <= 0;
			 
			 sum <= 0;
		end else begin		 
			 lev_a_1 <= y0 + (y1<<1);
			 lev_a_2 <= (y2<<2) + (y3<<3);
			 lev_a_3 <= (y4<<4) + (y5<<5);
			 lev_a_4 <= (y6<<6) + (y7<<7);
			 lev_a_5 <= -(y8<<8);
			
			 lev_b_1 <= lev_a_1 + lev_a_2;
			 lev_b_2 <= lev_a_3 + lev_a_4;
			 lev_b_3 <= lev_a_5;
			 
			sum <= lev_b_1 + lev_b_2 + lev_b_3;
		end
	end
	
	
	assign filtered_sig = sum[23:15];
	
endmodule
